@ Manchester (5 days/week)
Utilise your in-depth experience with Verilog to impact the microarchitecture specifications of display processors, defining RTL specifications, design and logic implementation and front-end implementation tasks like synthesis, logic equivalence check and STA. Work closely with the verification teams.
Knowledge required on ASIC/FGPA design methodology, IP signify methods especially timing/area/complexity trade-offs, AMBA, Perl, Tcl, C shell, MATLAB.
firstname.lastname@example.org – ref. #UT01